Deepen Your Expertise With the Industry's Most Comprehensive Conference Program

DesignCon's unmatched curriculum provides expert-led, hands-on training curated by our Technical Program Committee (TPC) — an expert panel of 99 industry professionals. With more than 100 technical paper sessions, panels, and tutorials spanning 15 tracks, DesignCon's three-day conference program covers all aspects of electronic design, including signal and power integrity; mixed-signal and high-speed serial design; system co-design; and test & measurement methodologies; and — new this year — machine learning. PLUS! You can acquire IEEE credit for every hour you spend at the conference. 

Session Formats

Boot Camps

Get up to speed, fast, with all-day Boot Camps covering core DesignCon concepts, including signal integrity, power integrity, and machine learning. See more »


DesignCon’s three-hour Tutorial Sessions offer rich learning opportunities on timely topics by allowing the speakers to cover crucial topics in greater depth. See more »

Technical Panels

These 40-minute Panel Discussions will host 3-5 visionaries as they weigh their insights on a carefully curated topic. There will be a moderator for each discussion. See more »

Technical Papers

Presented in 45-minute sessions, the Technical Papers aspect will address design case studies and application overviews from thought-leaders in the community.

Conference Tracks

Die, interposer, and packaging decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at die, interposer, and packaging levels, including SoC issues, multi-chip integration, and power delivery networks, plus related noise and jitter mitigation strategies.

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This track addresses challenges and solutions for design and verification that may involve various analog and algorithmic modeling abstractions and simulation approaches to predict critical aspects of system performance and reliability. Chip-to-chip data channels, clocks, and power delivery solutions each have specialized modeling requirements that must be met to accurately predict and deliver expected system performance. Accurate IBIS and IBIS-AMI models, for example, should include exploitation of the model’s features and benefits with full awareness of potential model limitations.

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Integrating photonics or wireless technology into electrical designs presents unique technical and design challenges whether at the chip, board, or system level. This track deals with the issues associated with emerging modulation schemes, complex 3D optical packaging, high data rate, high channel losses, nonlinear optics, thermal, and low power requirements and enables high performance and high data rate designs.

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This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

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This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

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High-speed data transfer up to 56-Gbps is supported by PCB platforms that typically constitute more than 80% of the channel length; memory subsystems and miscellaneous signals present their own unique design challenges. Along with all these, power and mixed-signaling requirements need to be simultaneously addressed. Will copper-based PCB platforms be able to take this to 112-Gbps? Can PCB support high current power management while maintaining noise margins needed to support sensitive devices? Using a wide range of EM modeling and PCB characterization techniques, this track explores effective high-speed signal and power design choices from backplanes and daughter cards to wearables and medical devices.

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The recent trends in data center, networking, cloud computing, mobile, autonomous driving, virtual/augmented reality, and high-performance computing (HPC) present great challenges in I/O interface designs. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various I/O interfaces.

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Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

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Jitter, noise, crosstalk, ISI, and reflection cause errors. Track 9 covers techniques for measuring, analyzing, and minimizing BER (bit error ratio), SER (symbol error ratio), and FER (frame error ratio), including simulation and modeling of signal impairments and techniques that optimize performance.

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High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, timing, detection, and FEC methods. This track covers design, modeling, analysis, and implementation of such techniques.

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Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling, and analysis on boards, packages, and chips. It emphasizes the modeling and analysis of impedance and/or supply noise and their impact on overall system performance.

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The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

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This track focuses on advancements in measurement techniques for all aspects of signal and power integrity, with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

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Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track covers signal integrity and signal conditioning analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

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The goal of this track is to enable fast, accurate design and verification of microelectronic circuits and systems by creating machine-learning algorithms to derive models for electronics and system design automation. Unlike traditional programming approaches that have knowledge embedded in complex algorithms and mathematical models, machine-learning uses simple algorithms and models, but with numerous parameters, that are intensively trained with complex data sets. This track explores applications where machine-learning approaches provide alternative solutions to traditional methods, and offer new solutions to challenging problems. Primary foci will be behavioral models, optimization for electronics design, and system analytics with machine learning techniques.

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Top 5 Reasons to Attend the Conference

Unlimited Track Hopping

Access any session across all 15 tracks to build the agenda that's right for you. That’s more than 100 hours of exclusive conference education to choose from! Full Agenda »

Leading Education

Get up to speed on key industry topics, including all levels of electronic design — chip, board, package, and system design. Full Agenda »

Expert Speakers

Learn from the brightest minds in the electronics design industry, focusing on signal and power integrity, test and measurement methodologies, and machine learning. Speaker Directory »

Networking Lunches

Swap insights and tips as you break bread with other serious professionals during the exclusive networking lunches. Available for Conference Pass holders only.

Welcome Reception - Sponsored by Keysight Technologies

Network with like-minded peers, re-connect with colleagues, and kick things off right at an exclusive welcome event on January 29, from 6–8 pm. Drinks, snacks, and entertainment will be provided. 

Need to Justify Your Attendance?

Justification Toolkit

Need help securing the budget or time off to attend DesignCon? We’ve created several resources for you.

Group Discounts

Save up to 25% when you register with a group of three or more! The more colleagues you bring, the more you save.

Contact Registration at [email protected] or call (888) 234-9476 or (415) 947-6135.

Bonus! Access Hours of Networking & Expo Events

The insights don’t stop when the conference sessions end. Your pass also gives you full access to the expo, including hourly presentations at the Keysight Education Forum, and Chiphead Theater sessions showcasing products and services from leading companies — plus access to more than 175 suppliers on the show floor.

Conference Hours

Tuesday, January 29
9:00 a.m.–6:00 p.m.

Wednesday, January 30
8:00 a.m.–5:00 p.m.

Thursday, January 31
8:00 a.m.–5:00 p.m.