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The DesignCon Conference Program

With more than 100 technical sessions, panel discussions, and tutorials spanning 15 tracks, DesignCon's three-day conference program covers every aspect of electronic design. Curated by our Technical Program Committee (TPC) — an expert panel of 99 industry professionals — the DesignCon curriculum is based on new research every year, making the conference an annual must-attend.

2019 Conference Tracks

All DesignCon content, including every track in the conference, is revised annually to include the latest research. Below are new elements to expect per track for 2019:

Die, interposer, and packaging decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at die, interposer, and packaging levels, including SoC issues, multi-chip integration, and power delivery networks, plus related noise and jitter mitigation strategies.

New for 2019:

  • Avoiding power-ground noise and SSO noise from degrading SI in the high-speed channel
  • Meeting HBM-unique system performance goals
  • Accurately modeling power noise induced jitter

More »

This track addresses challenges and solutions for design and verification that may involve various analog and algorithmic modeling abstractions and simulation approaches to predict critical aspects of system performance and reliability. Chip-to-chip data channels, clocks, and power delivery solutions each have specialized modeling requirements that must be met to accurately predict and deliver expected system performance. Accurate IBIS and IBIS-AMI models, for example, should include exploitation of the model’s features and benefits with full awareness of potential model limitations.

New for 2019:

  • Mitigating power and SI issues before they arise
  • Understanding channel simulation and the basic building blocks of equalization functionality

More »

Integrating photonics or wireless technology into electrical designs presents unique technical and design challenges whether at the chip, board, or system level. This track deals with the issues associated with emerging modulation schemes, complex 3D optical packaging, high data rate, high channel losses, nonlinear optics, thermal, and low power requirements and enables high performance and high data rate designs.

New for 2019:

  • New ways to provide lower-cost, more complex solutions for 5G and WiGig applications
  • Adding communications capability to low-cost temperature-tracking IoT devices
  • Whether TDECQ measurements can provide good correlation results

More »

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

New for 2019:

  • Meeting the tighter SI/PI/PD specifications for LPDDR5
  • Ways to achieve 100 Gbps C2M and DAC channels with standard industry technologies
  • How to overcome DDR5 simulation challenges

More »

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

New for 2019:

  • Finding the best values and variance for selected laminates in design simulations
  • How higher operating temperatures impact PCB materials performance
  • A tutorial covering how to more accurately predict losses of PCB structures before and after mass production

More »

High-speed data transfer up to 56-Gbps is supported by PCB platforms that typically constitute more than 80% of the channel length; memory subsystems and miscellaneous signals present their own unique design challenges. Along with all these, power and mixed-signaling requirements need to be simultaneously addressed. Will copper-based PCB platforms be able to take this to 112-Gbps? Can PCB support high current power management while maintaining noise margins needed to support sensitive devices? Using a wide range of EM modeling and PCB characterization techniques, this track explores effective high-speed signal and power design choices from backplanes and daughter cards to wearables and medical devices.

New for 2019:

  • Achieving the stringent cross-talk performance requirements for RFSoC SI applications
  • New methods to reduce fading from skew in PCB differential pairs of a SERDES link
  • How to obtain and apply the right material parameters in PCB interconnect modeling

More »

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, virtual/augmented reality, and high-performance computing (HPC) present great challenges in I/O interface designs. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various I/O interfaces.

New for 2019:

  • New bandwidth improvement techniques to enable the first 6.4 Gbps/pin LPDDR5 interface
  • A method to enable system tradeoffs in the design phase by accurately modeling bus turnaround SI dynamic
  • A tutorial on understanding memory architecture

More »

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

New for 2019:

  • New research on optimal TX and RX FFE partitioning to push system performance while minimizing power consumption
  • How to control P/N skew for successful PAM4 channel design
  • The best interconnect design practices beyond 56-Gbps PAM4 systems

More »

Jitter, noise, crosstalk, ISI, and reflection cause errors. Track 9 covers techniques for measuring, analyzing, and minimizing BER (bit error ratio), SER (symbol error ratio), and FER (frame error ratio), including simulation and modeling of signal impairments and techniques that optimize performance.

New for 2019:

  • Learn a faster than state-of-the-art methodology for simulation of baseline wander
  • How to evaluate degradation of high-speed serial link performance
  • A new way to speed up estimation of the data dependent jitter and the respective eye diagram

More »

High-speed communication systems require increasingly complex signal-processing techniques, including equalization, modulation, timing, detection, and FEC methods. This track covers design, modeling, analysis, and implementation of such techniques.

New for 2019:

  • Need-to-know information on the industry upgrade 50-Gbps per lane to the next-gen 100 Gbps per lane
  • Jitter effects on KP4 FEC gain in a PAM4 system
  • Requirements for PAM4 signaling over the OIF’s new 112 Gbps electrical interfaces for integrated photonic with the lowest possible power

More »

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling, and analysis on boards, packages, and chips. It emphasizes the modeling and analysis of impedance and/or supply noise and their impact on overall system performance.

New for 2019:

  • New research on design strategies for real platforms targeting automotive use cases
  • Power integrity planning and simulation for a 2048 processor compute card
  • A new methodology to specify performance-driven OTN VRM requirements

More »

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

New for 2019:

  • A different use of Huygens’ boxes to avoid RFI and desense in portable electronic devices
  • How to streamline regulatory testing of optical modules
  • A better way to predict field failure from small environmental stresses

More »

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity, with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

New for 2019:

  • Ways to avoid false-negative fails when implementing IEEE 802.3 PHY specifications
  • An improved understanding of the underlying physics that cause VNA instrumentation cables to limit high isolation measurements
  • A new way to measure the quality of transceivers for automotive Ethernet measurement applications

More »

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track covers signal integrity and signal conditioning analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

New for 2019:

  • How to pre-qualify your next PCB manufacturer
  • Measuring the effect and magnitude of etch factor on different practical applications not only for SI but also for PI
  • How COM analysis can provide a more refined solution for fully mapping 56/112G-PAM4 signaling

More »

The goal of this track is to enable fast, accurate design and verification of microelectronic circuits and systems by creating machine-learning algorithms to derive models for electronics and system design automation. Unlike traditional programming approaches that have knowledge embedded in complex algorithms and mathematical models, machine-learning uses simple algorithms and models, but with numerous parameters, that are intensively trained with complex data sets. This track explores applications where machine-learning approaches provide alternative solutions to traditional methods, and offer new solutions to challenging problems. Primary foci will be behavioral models, optimization for electronics design, and system analytics with machine learning techniques.

Brand new track for 2019:

  • A method to reduce the dimensions of tuning parameters and accelerate link optimization using ML based analysis
  • Reducing test time and cost per die with early noise analysis using a deep neural network
  • ML applications for simulation and modeling of 56 and 112-Gb SerDes systems
  • A full-day boot camp covering ML and artificial intelligence (AI) for hardware and electronics design

More »

Session Formats

Boot Camps

Get up to speed, fast, with all-day Boot Camps covering core DesignCon concepts, including signal integrity, power integrity, and machine learning. See more »

Tutorials

DesignCon’s three-hour Tutorial Sessions offer rich learning opportunities on timely topics by allowing the speakers to cover crucial topics in greater depth. See more »

Technical Panels

These 40-minute Panel Discussions will host 3-5 visionaries as they weigh their insights on a carefully curated topic. There will be a moderator for each discussion. See more »

Technical Papers

Presented in 45-minute sessions, the Technical Papers aspect will address design case studies and application overviews from thought-leaders in the community.

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Justification Toolkit

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Thank You to Our 2019 Conference Break Sponsor:

Conference Hours

Tuesday, January 28
9:00 a.m.–6:00 p.m.

Wednesday, January 29
8:00 a.m.–5:00 p.m.

Thursday, January 30
8:00 a.m.–5:00 p.m.