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The DesignCon 2019 Technical Program Committee (TPC) is comprised of 99 leading experts in all levels of electronic design — chip, board, package, and system. These accomplished engineers and executives from top companies such as Apple, Cadence, Cisco, Google, Intel, and Tektronix, rigorously review all call-for-paper submissions to develop a curriculum of the highest quality and industry relevance. The TPC maintains a strict standard for excellence year after year, and the Committee's dedication and expertise helps make DesignCon the nation's premier conference for chip, board, and systems design engineers.

2019 Technical Program Committee (TPC)

Brice Achkir, Distinguished Eng./Sr. Eng. Director, Cisco Systems
Joseph Aday*, Principal Electrical Engineer, Raytheon
Maria Agoston*, Principal Engineer, Tektronix
Ravinder Ajmani*, Technologist, Electronic Design, Western Digital
John Andresakis, Global Growth Leader- Circuits and Industrial Technology, Dow DuPont
Yianni Antoniades, Senior Staff EE, Winchester Electronics Corporation
Bruce Archambeault, EMC Engineer, MST
Pervez Aziz*, Senior Principal Engineer, Nvidia
Seungyong (Brian) Baek, SI Architect, Apple
Rula Bakleh, SI/PI Consultant, Teraspeed Consulting - A Division of Samtec
Heidi Barnes*, SI and PI Applications Engineer, Keysight Technologies
Dale Becker, Distinguished Engineer, IBM
Wendem Beyene*, Engineer, Intel
Luis Boluna, Sr. Applications Engineer, Keysight Technologies
Bradley Brim*, Product Engineer Architect, Cadence
David Brunker, Technical Fellow, Molex
Robert Carter*, Vice President of Technology and Business Development, Oak-Mitsui Technologies
Chris Cheng*, Distinguished Technologist, HP Enterprise
Sam Chitwood*, Product Engineer, Cadence
Daehyun Chung, Manager, Hardware Engineering, Nvidia
Antonio Ciccomancini Scogna, Principal Engineer, Samsung Electronics
Tom Cohen, Principal Engineer, Amphenol
Davi Correia, Signal Integrity Engineer, Carlisle Interconnects
O.J. Danzy, Senior Application Engineer, Keysight
Jan De Geest, Senior Staff SI R&D Engineer, Amphenol
Jay Diepenbrock, Consultant, SIRF Consultants, LLC
Vladimir Dmitriev-Zdorov, Principal Engineer, Mentor Graphics A Siemens Business
Greg Edlund, Senior Engineer, IBM
Jason Ellison*, Sr. Staff Signal Integrity Engineer, Amphenol
Paul Franzon, Cirrus Logic Distinguished Professor, Director of Graduate Programs, NCSU
Sanjeev Gupta, Product Architect, Intel
Sunil Gupta*, SIPI technical lead, Qualcomm Inc.
Robert Haller*, Sr. Principal Engineer, Extreme Networks
Gert Havermann, Signal Integrity Engineer, HARTING Stiftung & Co. KG
Allen F Horn III*, Research Fellow, Rogers
Rockwell Hsu, Technical Leader, Cisco Systems
Seunghyun Hwang, Sr. SI Engineer, Nvidia
Namhoon Kim, Chip Package Design Architect, Google
Ravi Kollipara, Technical Director, Apple
Beomtaek Lee, Senior Principal Engineer, Intel Corporation
Zhe Li, Hardware Engineer, Google
Joy Li*, R&D Manager, Cadence Design Systems
Mike Li*, Fellow, Intel
Cathy Liu*, Design Director, Broadcom Limited
Chris Loberg*, Sr. Marketing Manager, Tektronix
Om Mandhana, Staff Services AE, Cadence Design Systems
Henri Maramis*, President / CEO, Signata Corporation
Marko Marin, MBU Leader Signal Integrity, Infinera
Jon Martens, Fellow, Anritsu
Mike Mechaik*, Staff Application Engineer, Cadence Design Systems
Ted Mido, Principal R&D Engineer, Synopsys Inc
Martin Miller, Chief Scientist, Teledyne LeCroy
Jose Moreira*, Senior Staff Engineer, Advantest
Zhen Mu*, Product Engineering Architect, Cadence Design Systems
Jim Nadolny, Engineering Manager, Samtec
Alfred P. Neves*, Chief Technology Technologist, Wild River Technology
George Noh*, Director of Sales and Marketing, Holt Integrated Circuits
Istvan Novak, Senior Principle Engineer, Oracle
Dan Oh, Vice President, Samsung
Vishram Pandit*, Technology Lead (Signal/ Power Integrity), Intel
Jongbae Park, Principal Engineer, Apple
Peter Pupalaikis*, VP, Technology Development, Teledyne LeCroy
Fangyi Rao, Master Engineer, Keysight
Lee Ritchey, President, Speeding Edge
Gerardo Romo-Luevano, Sr. Staff Engineer/Manager, Qualcomm Technologies Inc
Steve Sandler, Managing Director, Picotest
Venkat Satagopan*, Sr. Staff Signal Integrity Engineer, Nvidia
Chris Scholz, Product Manager, Rohde & Schwarz
Christian Schuster, Professor, TUHH
Stefaan Sercu, SI R&D engineer, Samtec
Masashi Shimanouchi, SOC Design Engineer, Intel
Yuriy Shlepnev*, President, Simberian Inc.
Bert Simonovich, President, Lamsim Enterprises
Chad Smutzer, Senior Engineer, Mayo Clinic
Mike Steinberger, Lead Architect, Serial Channel Products, SiSoft
Ransom Stephens*, Signal Integrity Sage, Ransom's Notes
Suresh Subramaniam*, Engineering Director, Whizz Systems
Madhavan Swaminathan, John Pippin Chair Professor in Microsystems Packaging & Emag, Georgia Tech
Donald Telian, SI Consultant / Owner, SiGuys
Lars Thon*, Consultant, LT Engineering
Thomas To*, Technical Director, Xilinx
Peter Tomaszewski*, Sr Field Applications Engineer, Tektronix
Badhri Uppiliappan, Senior Staff CAD Engineer, Analog Devices
Ambrish Varma, Sr. Principal Software Engineer, Cadence Design Systems
Harald von Sosen, Scientist, Synopsys
Michael Vrazel, Systems and DV Manager, Texas Instruments
Min Wang*, Technical Lead Manager, Waymo
Scott Wedge*, Principal Engineer, Synopsys
Todd Westerhoff*, High Speed Design Product Marketing Manager, Mentor, A Siemens Business
Ken Willis, Product Engineering Director, Cadence
Markus Witte, System Engineer, Grimme
Randy Wolff, Principal Engineer - Silicon SI Lead, Micron Technology
Hsinho Wu*, Design Engineer, Intel
Ken Wu, Senior Hardware Engineer, Google
Chris Wyland*, Sr. Staff Hardware Engineer, Juniper Networks
Mobashar Yazdani*, Strategic Semiconductor Manager, Google
Iliya Zamek*, Consultant, ZI Consulting
Geoffrey Zhang, Distinguished Engineer and Supervisor, Xilinx
Pavel Zivny, System Engineer, Tektronix

*Indicates 2019 Track Co-chair