DesignCon is part of the Informa Markets Division of Informa PLC

This site is operated by a business or businesses owned by Informa PLC and all copyright resides with them. Informa PLC's registered office is 5 Howick Place, London SW1P 1WG. Registered in England and Wales. Number 8860726.

DesignCon Paper Awards recognize outstanding contributions to the educational goals of the DesignCon program. Papers are judged both on the merits of the written document and on the quality of their presentation. The awards serve to acknowledge the authors who receive them as leading practitioners in semiconductor and electronic design. The awards also provide incentive to authors to produce high-quality DesignCon papers and present them in a lucid and compelling manner.

DesignCon Paper Award recipients are selected through a two-step process. The first step is a review of the full-length papers accepted for the current year's program. Members of the DesignCon Technical Program Committee rank these papers based on quality, relevance, impact, originality, and commercial content, which determines the finalists for each award category. While selection as a finalist for a DesignCon Paper Award is a notable achievement in itself, winners are then chosen from the finalists based on the quality of their presentations as judged based on audience feedback collected during the conference.

2019 Best Paper Award Winners

Chip-Level Design

"Simulation & Measurement Correlation of Power Supply Noise Induced Jitter for Core & Digital IP Blocks"
Hyo-Soon Kang, Intel Corporation
Guang Chen, Intel Corporation
Ashkan Hashemi, Intel Corporation
Wern Shin Choo, Intel Corporation
David Greenhill, Intel Corporation
Wendem Beyene, Intel Corporation

"Top-Down Jitter Specification Approach for HBM System Optimization"
Hing “Thomas” To, Xilinx Inc.
Nanju Na, Xilinx Inc.
Anna Wong, Xilinx Inc.
Haixin Ke, Xilinx Inc.
Ajay Kumar Sharma, Xilinx Inc.
Wui Hung Moo, Xilinx Inc.

"A Review of Combiner/Divider PCB Design Topologies for 5G & WiGig ATE Applications"
Giovani Bianchi, Advantest
José Moreira, Advantest
Alexander Quint, Kalrsruhe Institute für Technologie

Board/System-Level Design

PCB Interconnect Modeling Demystified
Lambert (Bert) Simonovich, Lamsim Enterprises Inc.

Serial Link Design

"A Methodology for Performance Comparison of Center & Edge Sampling in Serial Links"
Hossein Shakiba, Huawei Canada – HiLink
Shayan Shahramian, Huawei Canada – HiLink
Behzad Dehlaghi, Huawei Canada – HiLink
David Cassan, Huawei Canada – HiLink
Davide Tonietto, Huawei Canada – HiLink

"100+ Gb/s Ethernet Forward Error Correction (FEC) Analysis"
Cathy Ye Liu, Broadcom Inc.

Power & RF Design

"A Fast & Simple RFI Mitigation Method without Compromising Signal Integrity"
Qiaolei Huang, Missouri University of Science and Technology
Ling Zhang, Missouri University of Science and Technology
Yang Zhong, Missouri University of Science and Technology
Jagan Rajagopalan, Amazon Lab126
Deepak Pai, Amazon Lab126
Chen Chen, Amazon Lab126
Amit Gaikwad, Amazon Lab126
Chulsoon Hwang, Missouri University of Science and Technology
Jun Fan, Missouri University of Science and Technology

"Using Multiple Huygens’ Boxes to Detect & Quantify the Coupling Path from Noise Source to Victim"
Antonio Ciccomancini Scogna, Futurewei Technologies Inc.
Jiangqi He, Futurewei Technologies Inc.
Cheng Wei Chang, Huawei
Liu Chen Jun, Huawei

"How the Braid Impedance of Instrumentation Cables Impact PI & SI Measurements"
Istvan Novak, Samtec
Jim Nadolny, Samtec
Gary Biddle, Samtec
Ethan Koether, Oracle

"Demistyfying Edge Launch Connectors"
Raul Stavoli, Carlisle IT
Davi Correia, Carlisle IT
Emad Soubh, Carlisle IT

2018 Best Paper Award Winners

Board/System-Level Design

"16Gb/s and Beyond with Single-Ended I/O in High-Performance Graphics Memory"
Tim Hollis, Micron Technology
Salman Jiva, Micron Semiconductor Products
Martin Brox, Micron Semiconductor
Wolfgang Spirkl, Micron Semiconductor
Thomas Hein, Micron Semiconductor
Dave Ovard, Micron Technology
Roy Greeff, Micron Technology
Dan Lin, Micron Technology
Michael Richter, Micron Semiconductor
Peter Mayer, Micron Semiconductor
Walt Moden, Micron Technology
Maksim Kuzmenka, Micron Semiconductor
Mani Balakrishnan, Micron Semiconductor
Milena Ivanov, Micron Semiconductor
Manfred Plan, Micron Semiconductor
Marcos Alvarez Gonzalez, Micron Semiconductor
Bryce Gardiner, Micron Technology
Dong Soon Lim, Micron Technology

"Statistical-Based RE DCD Jitter Analysis in High Speed NAND Flash Memory"
Sayed Mobin, Western Digital
Cindy Cui, Keysight Technologies

Serial-Link Design

"A Study of Forward Error Correction Codes for SAS Channel"
Haitao (Tony) Xia, Broadcom Ltd
Haotian Zhang, Broadcom Ltd
Aravind Nayak, Broadcom Ltd
Bruce Wilson, Broadcom Ltd
Jun Yao, Etopus

"Effective Link Equalizations using FIR, CTLE, FFE, DFE, and FEC for Serial Links at 112 Gbps and Beyond"
Hsinho Wu, Intel Corporation
Masashi Shimanouchi, Intel Corporation
Mike Peng Li, Intel Corporation

"Efficient Sensitivity-Aware Assessment of High-Speed Links Using PCE and Implications for COM"
Torsten Reuschel, Hamburg University of Technology
Ömer Yildiz, Hamburg University of Technology

Jayaprakash Balachandran, Cisco Systems Inc.
Cristian Filip, Mentor Graphics
Nitin Bhagwath, Mentor Graphics
Bidyut Sen, Cisco Systems Inc.
Christian Schuster, Hamburg University of Technology

"Feedforward Equalizer Location Study for High Speed Serial Systems"
Kevin Zheng, Stanford University
Boris Murmann, Stanford University
Hongtao Zhang, Xilinx 
Geoff Zhang, Xilinx

Power & RF Design

"40 GHz PCB Interconnect Validation: Expectations vs Reality"
Marko Marin, Infinera
Yuriy Shlepnev, Simberian

"A Causal Conductor Roughness Model and its Effect on Transmission Line Characteristics"
Vladimir Dmitriev-Zdorov, Mentor Graphics 
Bert Simonovich, Lamsim Enterprises 
Igor Kochikov, Mentor Graphics

"A NIST Traceable PCB Kit for Evaluating the Accuracy of De-Embedding Algorithms and Corresponding Metrics"
Heidi Barnes, Keysight Technologies
Eric Bogatin, Teledyne LeCroy
José Moreira, Advantest
Jason Ellison, The Siemon Company
Jim Nadolny, Samtec
Ching-Chao Huang, Ataitec
Mikheil Tsiklauri, Missouri University of Science and Technology
Se-Jung Moon, Intel Corporation
Volker Herrmann, Rohde and Schwarz

"Accurate and Fast RFI Prediction Based on Dipole Moment Sources and Reciprocity"
Qiaolei Huang, Missouri University of Science and Technology
Takashi Enomoto, Sony Global Manufacturing and Operations 
Shingo Seto, Sony Global Manufacturing and Operations
Kenji Araki, Sony Global Manufacturing and Operations
Jun Fan, Missouri University of Science and Technology
Chulsoon Hwang, Missouri University of Science and Technology

2017 Paper Award Winners

Chip-Level Design

"Characterizing and Selecting the VRM"
Steve Sandler, Picotest

Board/System-Level Design

"FastBER: A Novel Statistical Method for Arbitrary Transmitter Jitter"
Yunhui Chu, Intel Corporation
Alaeddin Aydiner, Intel Corporation
Kai Xiao, Intel Corporation
Beomtaek Lee, Intel Corporation
Dan Oh, Samsung Electronics
Oleg Mikulchenko, Intel Corporation
Adam Norman, Intel Corporation
Rob Friar, Intel Corporation
Charles Phares, Intel Corporation

"Non-Destructive Analysis and EM Model Tuning of PCB Signal Traces using the Beatty Standard"
Heidi Barnes, Keysight Technologies
José Moreira, Advantest
Manuel Walz, Advantest

"RX IBIS-AMI Model Silicon Correlation Metrics and Model Development Methodology"
Masashi Shimanouchi, Intel Corporation
Hsinho Wu, Intel Corporation
Mike Peng Li, Intel Corporation

Serial Link Design

"Exploring Efficient Variability-Aware Analysis Method for High-Speed Digital Link Design Using PCE"
Jan B. Preibisch, Technische Universität Hamburg-Harburg
Torsten Reuschel, Technische Universität Hamburg-Harburg
Katharina Scharff, Technische Universität Hamburg-Harburg
Jayaprakash Balachandran, Cisco Systems Inc.
Bidyut Sen, Cisco Systems Inc.
Christian Schuster, Technische Universität Hamburg-Harburg

"Investigation of Mueller-Muller CDR Algorithms in PAM4 High speed Serial Links"
Yuhan Yao, Oracle Corporation
Xun Zhang, Oracle Corporation

Dawei Huang, Oracle Corporation
Jianghui Su, Oracle Corporation
Muthukumar Vairavan, Oracle Corporation
Chai Palusa, Oracle Corporation

"PCIe Gen4 Standards Margin Assisted Outer Layer Equalization for Cross Lane Optimization in a 16GT/s PCIe Link"
Mohammad S. Mobin, Broadcom Ltd
Haitao Xia, Broadcom Ltd
Aravind Nayak, Broadcom Ltd
Gene Saghi, Broadcom Ltd
Christopher Abel, Broadcom Ltd
Lane Smith, Broadcom Ltd
Jun Yao, Broadcom Ltd

Power & RF Design

"Cost-effective PCB Material Characterization for High-volume Production Monitoring"
Yongjin Choi, Hewlett-Packard Enterprise
Christopher Cheng, Hewlett-Packard Enterprise
Yasin Damgaci, Hewlett-Packard Enterprise
Nagaraj Godishala, Hewlett-Packard Enterprise
Yuriy Shlepnev, Simberian

"Overview and Comparison of Power Converter Stability Metrics"
Joseph ‘Abe’ Hartman, Oracle
Alejandro 'Alex' Miranda, Oracle
Kavitha Narayandass, Oracle
Alexander Nosovitski, Oracle
Istvan Novak, Oracle

"RFI and Receiver Sensitivity Analysis in Mobile Electronic Devices"
Antonio Ciccomancini Scogna, Samsung Electronics Mobile Division, HE Group
Hwanwoo Shim, Samsung Electronics Mobile Division, HE Group
Jiheon Yu, Samsung Electronics Mobile Division, HE Group
Chang-Yong Oh, Samsung Electronics Mobile Division, HE Group
Seyoon Cheon, Samsung Electronics Mobile Division, HE Group
NamSeok Oh, Samsung Electronics Mobile Division, HE Group
Dong Sub Kim, Samsung Electronics Mobile Division, HE Group

2016 Paper Award Winners

High-Speed Signal Design

"A Versatile Spectrum Shaping Scheme for Communicating Beyond Notches in Multi-Drop Interfaces"
Ali Hormati, Kandou Bus, Switzerland 
Armin Tajalli, Kandou Bus, Switzerland 
Christoph Walter, Kandou Bus, Switzerland 
Kiarash Gharibdoust, EPFL, Switzerland 
Amin Shokrollahi, Kandou Bus, Switzerland

"Mid-Frequency Noise Coupling Between DC-DC Converters and High-Speed Signals"
Laura Kocubinski, Oracle 
Gustavo Blando, Oracle 
Istvan Novak, Oracle

Memory & Parallel Interfaces

"Analysis and Verification of DDR3/DDR4 Board Channel Impact on Clock Duty-Cycle-Distortion (DCD)"
GaWon Kim, Altera 
June Feng, Altera 
Marjan Mokhtaari, Altera 
David Lieby, Altera 
Janmejay Adhyaru, Altera 
Balaji Natarajan, Altera 
Dan Oh, Altera

"Optimal DDR4 System with Data Bus Inversion Feature in FPGA High Speed High Bandwidth Memory Interface"
Thomas To, Xilinx 
Changyi Su, Xilinx 
Juan Wang, Xilinx 
Penglin Niu, Xilinx 
Yong Wang, Xilinx

Test & Measurement

"Jitter, Noise Analysis and BER Synthesis on PAM4 Signals on 400 Gbps Communication Links"
Maria Agoston, Tektronix
Mark L. Guenther, Tektronix

Richard J. Poulo, Tektronix
Kalev Sepp, Tektronix
Pavel Zivny, Tektronix

"BER- and COM-Way Channel Compliance Evaluation: What are the Sources of Difference?"
Vladimir Dmitriev-Zdorov, Mentor Graphics 
Cristian Filip, Mentor Graphics 
Chuck Ferry, Mentor Graphics 
Alfred P. Neves, WildRiver Technology

"A New Characterization Technique for Glass Weave Skew Sensitivity"
Eric Bogatin, Teledyne LeCroy 
Bill Hargin, Nan Ya Plastics 
Vinit Sonawane, Univ. of Colorado, Boulder 
Sanket Sapre, Univ. of Colorado, Boulder 
Vidyadhar Yashwant Deodhar, Univ. of Colorado, Boulder 
Nikhil Joshi, Univ. of Colorado, Boulder 
Anand Ursekar, Univ. of Colorado, Boulder

Power Integrity

"Impacts of Dynamic Noise in Multi-Core or SOC Designs" 
Yujeong Shim, Altera 
Dan Oh, Altera

"Electrical and Thermal Consequences of Non-Flat Impedance Profiles"
Jae Young Choi, Oracle 
Ethan Koether, Oracle 
Istvan Novak, Oracle

"Chip and Package-Level Wideband EMI Analysis for Mobile DRAM Devices"
Jin-Sung Youn, Samsung Electronics
Jieun Park, Samsung Electronics 
Jinwon Kim, Samsung Electronics 
Daehee Lee, Samsung Electronics 
Sangnam Jeong, Samsung Electronics 
Junho Lee, Samsung Electronics 
Hyo-Soon Kang, Samsung Electronics 
Chan-Seok Hwang, Samsung Electronics 
Jong-Bae Lee, Samsung Electronics