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Gather new methods and techniques from the experts at Keysight Technologies during their FREE education workshops—see below schedule. Visit booth #725 on the Expo Floor to find out more about their latest products, services, and offerings!

Location: Great America 1

DAY 1 - Wednesday, January 30

Right on the heels of DDR4, the industry’s next generation of system and mobile memories will drive another paradigm shift for Silicon and system developers. DDR4 required thinking to move beyond the certainty promised by setup and hold timings and voltage margins into the new terrain of random and deterministic jitter and noise as well as bit error rates (BER) that could never be guaranteed to be zero no matter how much margin you had. This is the world of data eyes and statistics. Before DDR4 speeds can be doubled, the statistical eye that people were just getting their minds wrapped around will collapse. Opening it back up requires applying concepts first developed for high speed serial busses like PCI Express to DDR. Memory’s wide, single ended, bidirectional and bursty bus stretches these concepts to their limits and beyond, requiring everyone to up their game. This session will show you how to get your game on so you can master a whole new generation of DRAM.

Speaker:
Perry Keller, Lead Digital Applications and Standards Program, Memory Applications Program Manager, Keysight Technologies

Only two years in the making, PCI Express 5.0 is quickly following on the heels of the PCIe 4.0 specification and is expected to be finalized in H1 2019. At speeds of 32GT/s, and across channels that conspire to attenuate the 32GT/s signal by up to -38dB of loss at 16Ghz, PCIe 5.0 portends to become the most challenging edition of the PCI Express standard to date. In this session you will learn about some of the key differences between PCI Express 5.0 and PCie 4.0 including changes to the Gen5 receiver equalization requirements along with new options for link equalization. Especially challenging for Gen5 is the need to be able to tolerate a eye height of just over 10mV which is expected to push receiver technology to the brink. In this session you’ll learn not only what’s new with the PCIe 5.0 standard but also what to look for as you evaluate tools to help you evaluate your transmitter and receiver circuits.

Speakers:
Rick Eads, Principal Program Manager for Serial Computer Bus Technologies, Keysight Technologies
Thorsten Goetzelmann, Application Engineer Receiver Test, Keysight Technologies

The USB Type-C connector has significant adoption with standards like USB, Thunderbolt, DP, and HDMI utilizing this connector.

This session will review requirements for testing USB 3.2 and next-gen Type-C technologies. As faster signals get sent through more Type-C wires and longer cables, new measurement techniques are required to test repeaters, active cables, and also comprehend crosstalk. We will review these new measurement solutions and ultra-low noise test instruments required to properly characterize these next-gen signals.

NOTE: USB Type-C™ and USB-C™ are trademarks of USB Implementers Forum. Thunderbolt™ and the Thunderbolt logo are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

Speaker:
Jit Lim, Standards and Solutions Lead for USB and Thunderbolt, Keysight Technologies

Most of work on the '400G Class' Standards is complete, and new projects are starting to define the electrical links that will enable the next '800G Class' of optical and electrical standards. The low margins we see today will be even smaller or non-existent in the next generation. Verifying compliance for 400G requires careful attention to test setup and execution, and will likely require even more discipline moving forward. This session will cover practical techniques to minimize some of the problem areas users are experiencing today in validating compliance in 400G links, and what challenges we may see as the 800G class Standards begins to take shape.

Speakers:
Steve Sekel, 400G Solutions Specialist, Keysight Technologies
Robert Sleigh, Strategic Product Planner, Keysight Technologies

DAY 2 - Thursday, January 31

Fifth-generation mobile technology is causing a lot of excitement in the telecommunications industry. The next generation in mobile communications promises much higher data rates, significantly lower latencies, smaller cells and a much higher number of active users per cell. The new 5G technology may even be revolutionary in enabling many new applications. Good news for the communication business is that future 5G mobile networks will require even more digital and photonic technologies than already used by its legacy 4G and 3G predecessors. The presentation will focus on the expected impact that future 5G mobile networks may have on the physical layer from server to fronthaul.

Speaker:
Beate Hoehne, Business Development Manager, Internet Infrastructure Networks and Data Centers, Keysight Technologies

Hyperscale data centers are a critical component of today's internet infrastructure. This architecture requires extreme bandwidth over everything copper and demands next level design techniques and analysis tools in the signal integrity lab. This presentation will clarify how to achieve the highest practical Signal Integrity (SI) of the physical layer by analyzing an example channel with mixed-mode S-parameters, eye diagram, time domain reflectometry (TDR) and single pulse response in both simulation and measurement. In addition, a case study for PCI express will demonstrate the usage of IBIS-AMI models with equalization on both transmitter and receiver. After fabricating and measuring the example channel, SI analyses will be shown to demonstrate the importance of a robust SI measurement and simulation workflow. If you are new to signal integrity, this session will give you a head start on your signal integrity journey, including a complimentary example files for continuing your learning. For experienced SI engineers, this presentation is an excellent refresher on the fundamental SI analyses and concepts in both simulation and measurement.

Speakers:
Mike Resso, Signal Integrity Application Scientist, Keysight Technologies
Tim Wang Lee, Application Engineer for High Speed Digital applications in the EEsof EDA Group, Keysight Technologies

One of the challenges for the practical realization of quantum computers is the classical control of the individual qubits. Generally speaking, this classical controller needs to generate and acquire long sequences of microwave and DC pulses in order to initialize the qubits, execute the quantum algorithms (gates), and perform the readout of the result. All these pulses need to be generated with perfect real-time control, inter-channel synchronization, and must be phase-coherent. In addition, fast feedback loops are needed to perform quantum error correction much faster than the coherence time of the qubits. All those challenges can only be addressed with cutting-edge scalable microwave electronics and comprehensive software tools.

Speaker:
Marc Almendros, Quantum Engineering Solutions (QES) | General Manager, Keysight Technologies

The insatiable desire for more bandwidth in data centers has led to intense pressure to push DDR5 memory technology out to market faster. Eagerly anticipated to release in 2019, DDR5 is expected to have twice the data rate of DDR4. For high-speed PCB designs, both DDR4 and DDR5 are not without challenges and significant risks as design margins shrink quickly. During this webinar you will learn how to cut through the complexity of setting up simulations for DDR. We'll show you how to approach a practical design and analysis workflow for DDR4, and ready yourself for DDR5. Furthermore, you will better understand the simulation and modeling eco-system and how compliance measurements can be used to deliver a more predictable design flow and reduce time-to-market.

Key Learnings:
1. Learn how to cut through simulation complexity
2. Gain an understanding of design challenges and the IBIS-AMI modeling eco-system
3. Learn how to use simulation tools to prepare yourself for DDR5 designs now

Speaker:
Stephen Slater, High-Speed Digital Simulation Product Manager, Keysight Technologies