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Technical Papers, Panels, Tutorials, and Boot Camps

Santa Clara Convention Center, January 28 – 30, 2020

Extended Abstract Deadline: July 26, 2019

Papers Due in mid-November 2019

We are pleased to announce this Call for Technical Papers, Panels and Tutorials for DesignCon 2020, the premier educational conference and technology exhibition for semiconductor and electronic design engineers. At DesignCon, engineers talk to engineers to find practical solutions to the challenging problems they share in design and verification. We emphasize education and peer-to-peer sharing among practicing engineers, creating a unique atmosphere for learning about state-of-the-art design methodologies and technologies. Individuals presenting papers at DesignCon will join an elite group offering leading-edge case studies, technology innovations, practical techniques, design tips, and application overviews.

We solicit abstracts for three types of sessions: technical papers, technical panels, and tutorials. Technical papers, which are up to 25 pages long, address design case studies and application overviews and are presented in 45-minute sessions. Technical panels are 75-minute presentation/discussion sessions featuring 3-5 panelists plus a panel chair to moderate the discussion. Tutorials are 3-hour sessions (papers up to 50 pages long are optional), allowing the speakers to cover topics in greater depth. Tutorials are scheduled for Tuesday, January 28; the technical paper sessions will be held on Wednesday–Thursday, January 29 –30; technical panels are scheduled on Tuesday-Thursday at the end of each day’s program.

You may also submit a proposal for a full-day Boot Camp or a Chiphead Theater presentation. Boot Camps provide an in-depth introduction to core DesignCon concepts such as Signal Integrity, Power Integrity, PCB Fabrication, and Test & Measurement. Please note that, due to the full-day format, there are a very limited number of Boot Camp slots. Chiphead Theater sessions provide less-technical content such as teardowns, demos, and panels presented as 45-minute sessions on the expo floor and open to all attendees.

To Submit a Proposal

Prepare the following information and submit ONLINE by extended deadline July 26, 2019:

  • Title of submission
  • Conference track preference (required), secondary track preference (optional). (Reviewers may move your submission to a more appropriate track based on the content provided in the submission)
  • Session format: 45-minute technical paper, 75-minute panel discussion, or 3-hour tutorial (If you have a secondary format preference, please note in the comments)
  • Audience level (introductory, all, or advanced, REQUIRED) – prerequisites required for advanced
  • Key takeaways (50 words max, REQUIRED) – for use on conference web site and mobile app if accepted
  • Abstract (100 words max, REQUIRED) – for use on conference web site and mobile app if accepted
  • Extended abstract (500 words max, REQUIRED) – for use by reviewers to judge your proposal
  • Purpose statements (REQUIRED) – please provide (1) problem statement, (2) what’s new statement, and (3) deliverables statement to assist the reviewers in understanding the practical application of the information to be presented in your paper
  • Prerequisites (50 words max) –required for advanced audience levels
  • Keywords: Provide relevant keywords
  • Comments (optional) – additional information for reviewers and staff in their consideration of your proposal
  • Authors can upload supplemental documents to support their proposal (optional)

Review Criteria

The DesignCon 2020 Technical Program Committee reviews all submissions based on quality, relevance, impact, and originality. Prospective authors are welcome to reference products as long as product references add to the educational value and are presented in an appropriately non-commercial fashion.

  1. Quality – DesignCon papers, panels, and tutorials should be well organized and easily understood. The abstract and summary are judged as indicators of what can be expected of the paper or session.
  2. Relevance – The proposed paper, panel, or tutorial should be highly relevant to the interests of the DesignCon audience in general and the track topic in particular.
  3. Impact – DesignCon papers, panels, and tutorials should contribute to the educational mission of DesignCon. Submissions reporting on important results, methodologies, or case studies of special significance will be considered favorably. Submissions on related standards activities are welcome.
  4. Originality – Reports on new design methodologies, case studies for innovative designs, or other novel results contribute to the DesignCon goal of providing a high-quality educational program for practicing engineers. However, outstanding proposals on "classic" or "introductory" topics will also be viewed favorably.
  5. Commercial contentProduct promotion is not permitted in DesignCon technical sessions. Evidence of product promotion in a paper, panel, or tutorial proposal will lead to rejection of the proposal. It is acceptable to use a product in a design case study or as a proof of concept for a design methodology.

Note: The DesignCon Technical Program Committee reserves the right to request edits to submitted papers, or to reject a submitted paper if it fails to match the accepted abstract or above guidelines.

2020 Tracks

Below is a description of each DesignCon 2020 Track, along with sample topics. All relevant proposals—including topics other than those listed—will be considered

Please note that the track numbers have changed. In order to make our track topics more clearly differentiated, we have reorganized the order of the tracks. The former track 6 has been merged into tracks 5 and 14 and track order has been changed.

Die, interposer and packaging decisions can make or break the high-performance interface. This track covers a wide variety of signal and power integrity topics at die, interposer, and packaging levels, including SoC issues, multi-chip integration, and power delivery networks, plus related noise and jitter mitigation strategies.

Sample topics

  • Signal integrity (SI), power integrity (PI), and power distribution network (PDN) considerations in chip and packaging designs
  • Implications of chip-level decisions on systems design (e.g. frequency, timing, design overhead, voltage)
  • On-chip and chip-to-chip interconnect design and analysis
  • 2.5D/3D interconnects and interposer design
  • Simultaneous switching noise (SSN) and crosstalk suppression techniques
  • On-chip instrumentation and measurement
  • On-chip current modeling and correlation
  • On-chip noise-to-jitter modeling and circuit implications/strategies
  • Multi-voltage and power-gating design for SOCs and circuit-level implications
  • Low-power strategies and implementation
  • Circuit and interface calibration techniques
  •  Clock and reset strategies
  • 2.5D/3D interconnect and interposer design as applied to die/interposer/package technology
  • Through-silicon vias (TSV)
  • SIP partition and IP integration
  • On-chip and chip-to-chip interconnect design and analysis within a package
  • Pre-silicon and post-silicon validation and verification

This track addresses challenges and solutions for design and verification that may involve various analog and algorithmic modeling abstractions and simulation approaches to predict critical aspects of system performance and reliability. Chip-to-chip data channels, clocks, and power delivery solutions each have specialized modeling requirements that must be met to accurately predict and deliver expected system performance. Accurate IBIS and IBIS-AMI models, for example, should include exploitation of the model's features and benefits with full awareness of potential model limitations.

Sample topics

  • IBIS-AMI model generation, validation and simulation strategies
  • Practical electrical vs. algorithmic partitioning for successful modeling
  • Handling PVT corners within IBIS and AMI models
  • Power-aware IBIS modeling for SSO simulation
  • Guidelines for achieving consistent results with different simulation tools
  • Faster channel simulation approaches; SPICE, Statistical, System
  • SPICE vs. IBIS modeling and SPICE-to-IBIS tradeoffs
  • AMI model extraction from data-sheet parameters
  • IBIS-AMI model quality and silicon correlation methodologies
  • Methods for converting Verilog or MATLAB models to IBIS-AMI
  • Design and IBIS simulation with repeaters and re-timers
  • Analog/mixed signal and power design methods
  • Case studies of achieving trustworthy compliance testing through simulation
  • Mixed-signal behavioral models for SerDes phase-locked loops
  • Approaches for system-level modeling of I/O buffers and voltage regulators
  • Behavioral modeling of clock jitter and phase noise
  • Simulation of reliability gain/loss by different power topology selection
  • Analog/mixed signal and power models and simulation
  • Digital Controllers and compensators for Voltage control, modeling, and correlation
  • Chip-level modeling of power controllers and drivers for PDN simulations
  • Using PDN simulations to validate power management strategies

Integrating photonics or wireless technology into electrical designs presents unique technical and design challenge whether at chip, board, or system level. This track deals with the issues associated with emerging modulation schemes, complex 3D optical packaging, high data rate, high channel losses, nonlinear optics, thermal, and low power requirements and enables high performance and high data rate designs.

Sample topics

  • Technology:
    • Techniques to bring together high-speed
      electrical and high-speed optical circuits
    • Microwave photonics
    • Photonic ICs
    • Data Communication, Lidar and Sensors
    • RF/Mmwave Design
    • Wireless interconnect technologies
    • Techniques to bring together high-speed electrical and mmwave wireless circuits
    • 5G and WiGig
  • Link & Interconnect:
    • Photonic interconnects
    • Link design
    • Link impairments
    • Mmwave wireless links
  • Design, Layout & Assembly
    • Passive components for 100 Gbps/400 Gbps optical communications.
    • Photonic integration and packaging design
  • Modeling & Simulation
    • Silicon Photonics passive components such as optical waveguides, transitions, mode converters, phase rotators.
    • Silicon Photonics phase shifters, attenuators, MZM and ring modulators
    • Lasers and photo detectors
    • Optical phase array antenna
    • Mmwave Antenna array modeling and simulation
  • Compliance & measurements
    • Measurement and testing of optical/electrical ICs
    • Dealing with coexistence issues when integrating optical and/or wireless transmission, e.g. EMI, integration
    • Optical signal processing
    • Wireless and optical network convergence
    • Layout considerations for RF circuits, photonic circuits
    • Silicon nanophotonics
    • High-speed wireless options
    • FCC qualification; interference mitigation Integrated optical links, optical interconnects
    • Integration of optical subsystems
    • Measurement and testing of RF/mmwave ICs
    • Over the Air Testing (OTA) testing of Antenna in package (AIP) devices.
    • Correlation between volume production testing and anechoic chamber standard mandated measurements.

This track considers how printed circuit board (PCB) materials and fabrication processes can affect the electrical properties and performance of the circuitry mounted on the board.

Sample topics

  • Advanced laminate and PCB processing
    • Resin to copper adhesion techniques
    • Fine registration improvements
    • Advanced stub mitigation including backdrilling
    • Embedded devices (active and passive)
    • Passive and active devices (surface mount)
    • Embedded optical channels
  • Decoupling with Embedded Capacitor layers Advanced interconnects including conductive and dielectric materials
    • Accurately predicting path losses
    • Impact of copper on characterization and design
    • Microvias, RF vias and thermal vias
    • High aspect-ratio vias
    • What materials should I choose?
    • Routing Techniques
    • Materials for optical waveguides
    • Sockets and connectors
  • 3D Printing and Additive Manufacturing
  • Next Generation Materials
    • Advances in low loss laminates
    • Advances in copper surfaces
    • Advances in thin dielectrics
  • Rigid-flex and multilayer flex circuit materials, design and manufacturing
  • Glass weave effects on signal quality and techniques to mitigate
  • Materials characterization and modeling
  • Creative techniques to implement next generation technology in high volume production
  • Trade-offs in SI/PI/Timing Integrity
    • Impact on costs and techniques to reduce cost
  • Thermal characterization and modeling
  • PCB and hybrid media advances for increased power delivery and thermal management
  • How to identify and eliminate materials-/manufacturing-related skew in very high-speed differential paths
  • Design challenges for wearable electronics
    • Material/dielectric modeling and characterization
    • Simulation accounting for change in material e.g., when flexed or bent
  • Advances in high-speed conductive surface modeling
  • Copper roughness modeling and characterization
  • Broadband dielectric and conductor characterization (e.g., loss and dispersion, roughness, anisotropy, fiber weave effect)
  • Dielectric, conductor and conductor roughness model parameters identification

The recent trends in data center, networking, cloud computing, mobile, autonomous driving, machine learning, virtual/augmented reality, and high-performance computing (HPC) present great challenges in I/O interface designs. Interface design also needs to meet increased bandwidth requirements while reducing power, cost, form factor, and maintaining or reducing latency. This track addresses the latest design techniques and signal and power integrity solutions to meet these requirements for various I/O interfaces.

Sample topics

  • 2.5D/3D/SiP interface
    • HBM, HMC and Wide I/O interfaces
    • Proprietary or emerging 2.5D/3D/SiP I/O interfaces
  • Memory interface
    • Mobile memory designs (LPDDR, DDR-NAND, UFS)
    • Mainstream memory designs (DDR, GDDR, RLDRAM)
    • NV memory
    • Emerging memory interface (optical memory)
  • High-speed parallel interface
    • Standards-based designs (e.g. HyperTransport 3.0, PCI-X, SPI 4.2, MIPI)
    • Parallel interconnect signal conditioning techniques (e.g. CTLE, DFE)
    • Low-power designs
  • Signal/power integrity simulation
    • Supply noise induced clock and data jitter analysis
    • Channel crosstalk, simultaneous switching noise, and statistical timing models

This track covers a broad range of topics addressing design-oriented modeling simulation and analysis for cost-effective power and signal integrity (SI) performance optimization of chip/package/board/chip+package+board for modern microprocessor/digital systems.

Sample topics

  • Design case studies (automotive electronics, biomedical electronics, communications, consumer electronics, industrial/home automation, mobility applications)
  • System issues affecting PCB/package/chip/device power modeling
  • Interaction of protection devices
  • Application Specific end-to-end system modeling
  • New technology design, including IoT design and 5G system co-design
  • First- and second-level interconnect analysis as it affects system performance
  • Sub-system interaction
  • System-level power and signal integrity
  • Buffer modeling for system simulation
  • System co-design for high-speed signaling
  • I/O interoperability
  • Mixed-signal system design
  • System-level challenges of multi-voltage design
  • System-level modeling and measurement
  • System-in-package (SiP), multi-chip package (MCP), module design
  • 3D/2.5D on-chip interconnect design and analysis, heterogenious die
  • Performance trade-offs: electrical, mechanical, thermal

Systems designers must resolve a complex set of tradeoffs among package/board/backplane design, choice of connector/materials, SerDes transmit/receive equalization capabilities, and signal coding schemes to get the high-speed serial channels in their system to meet both performance and cost requirements. This track presents system analysis techniques, design studies, and technology/performance data to help system designers make design and technology choices that are as effective as possible.

Sample topics

  • Design, architecture and/or SI analysis of complete backplane and cable interconnect systems
  • Backplane and cable signal conditioning
  • Copper vs. fiber trade-offs
  • Design verification and validation
  • Ethernet architectures
  • IBIS algorithmic modeling interface (AMI) applied to end-to-end channel analysis
  • Physical modeling and simulation
  • SerDes design techniques
  • System interconnect architecture
  • Switch-fabric architectures
  • PAM-N vs NRZ vs other advanced modulation schemes system trade-offs/case studies
  • Serial link system performance evaluation techniques (e.g. COM, Salz SNR)
  • End-to-end serial link design/idea that optimizes link performance and latency while meeting reach and power requirements
  • Serial link system performance optimization techniques

Jitter, noise, crosstalk, ISI, and reflection cause errors. Track 9 covers techniques for measuring, analyzing, and minimizing these, as well as BER/SER/FER (bit/symbol/frame error ratio). Also covered are simulation and modeling of signal impairments and techniques that optimize performance.

Sample Topics:

  • Error ratio, SNDR (signal-to-noise-distortion ratio), level-mismatch/non-linearity and distortion analysis, measurement, and simulation
  • Measurement and estimation for:
    • Closed eye analysis via CTLE/FFE/DFE/CDR, and COM
    • Jitter and noise simulation, analysis, and measurement
    • Stochastic and deterministic, correlated and uncorrelated jitter, noise, crosstalk, reflection, and ISI (inter-symbol interference) modeling techniques
  • PAM4 signal measurement, analysis, and BER/SER/FER minimization
  • Machine learning (ML) and AI techniques for minimizing noise, jitter, and BER
  • Relationship between S-parameters and time domain errors, e.g. ERL (effective return loss)
  • Jitter and noise test and measurement for diagnostics and standards compliance
  • Time/frequency domain, phase noise, and white and colored jitter/noise spectrum analysis and prediction
  • Stressed eye testing: Jitter and interference calibration, tolerance measurement
  • Embedded/forward clocking and related jitter mitigation techniques
  • BER/SER/FER analysis, modeling, and optimization in the presence of FEC (forward error correlation) for Gaussian and burst errors
  • Channel/test fixture de-embedding and modeling

High-speed communication systems require increasingly complex signal-processing techniques; including equalization, modulation, synchronization, timing, detection, and FEC methods. This track covers design, modeling, analysis, and implementation of such techniques.

Sample topics

  • Active/passive pre-emphasis and equalization
  • Adaptive tap optimization
  • CDR and PLL algorithms, modeling and realization
  • Digital pre-emphasis and equalization
  • FEC (forward error correction)
  • End-to-end channel analysis
  • Comparing simulation and measurement
  • Eye diagram compliance testing
  • IBIS algorithmic modeling interface (AMI) applied to evaluating SerDes performance
  • SerDes device simulation
  • Verification by measurement
  • Advanced modulation (PAM-n, QAM/coherent, Trellis Coded Modulaton (TCM), etc)
  • Pseudo random data pattern and its frequency spectra
  • Signal coding, scrambling and DC balance modeling
  • Signal detection algorithms
  • Signal modeling and measurement
  • Simulation algorithms, e.g. simulation of signal-processing algorithms
  • Back-channel training methods and performance
  • Carrier synchronization for coherent systems

Panel topic suggestion:
In-the-box optical links: Are they needed for the next speed node past 112Gbps, and if so, what are the implications for signal processing, equalization and coding?

Power Integrity, distribution, and management are essential for system functionality and performance. This track addresses power regulation in terms of power distribution network design, modeling and analysis on boards, packages, and chips. It emphasizes the modeling and analysis of impedance and/or supply noise and their impact on overall system performance.

Sample topics

  • System level PDN design strategy
    • Chip/package/board analysis and decoupling optimization
    • PDN performance versus cost, size, yield, reliability, etc.
    • PDN specifications
    • System and PCB PDN modeling and simulation
    • PDN specifications, measurements, and correlation
    • System power noise and transients modeling and mitigation
    • Supply noise induced jitter analysis and optimization
  • Chip-level power distribution and regulation impact on system PDN performance
    • On-chip power grid inductance, resistance, and on-die decoupling
    • Dynamic and static voltage variations
    • On-chip regulator and power gating impact on power integrity
  • Power supply design
    • DC/DC converter and VRM design including GaN technology
    • Power supply design, dynamic response
    • Power efficiency management strategies
    • Power-aware architecture
    • Power modes management for portable & mobile electronics
    • Wireless power transfer
    • Digital control loops
    • Low-voltage, high-power designs
    • VRM modeling and simulation

The electromagnetic compatibility (EMC) and interference (EMI) track aims to cover topics related to the electrical modeling, simulation, design, and validation for product compliance and certification due to EMI/EMC issues. This track raises the awareness and the impact for design and systems engineers in order to mitigate possible issues in the early design stage.

Sample topics

  • Design techniques to reduce or eliminate sources of EMI
  • Near-field and far-field radiation computations
  • Near-field and far-field radiation scan
  • EMI radiation and suppression
  • EMI system susceptibility
  • Near-field coupling and crosstalk
  • Emissions and interference modeling
  • Noise characterization and containment
  • EMI troubleshooting techniques
  • Pre-qualification testing for immunity (radiated, ESD, etc.)
  • Pre-qualification testing for emissions
  • Shielding at PCB, package, and system level
  • EMI measurements and measurement techniques
  • New shielding techniques and novel shielding materials
  • Meeting compliance requirements
  • RFI/De-sense for mobile electronic devices
  • Power supply consideration for EMI/RFI
  • EMI for high-density multi-port systems
  • ESD modeling

This track focuses on advancements in measurement techniques for all aspects of signal and power integrity with an emphasis on understanding the practical limitations and quality of the measurement as well as the accuracies involved when trying to match simulations with measurements.

Sample topics

  • Measurement methodologies for Signal Integrity, Power Integrity, and EMI/EMC
  • Standards-based measurement methods for compliance with PAM4, Ethernet, PCIe, USB, DDR, etc.
  • S-Parameter quality, causality, and passivity of measurement calibration methods
  • Passive device-measurement methods for on-die, package, connector, board testing
  • Power supply noise measurement methods for dynamic load response, ripple injection…
  • Active device measurement methods for gigabit I/O, on-die instruments, SOC testing, etc.
  • Signal integrity of fixture design for PCB, connectors, package, on-die, measurements.
  • Fixture de-embedding techniques including EM-solver and measure based models
  • Fixture design topologies including probing, interposer test vehicles, PCB, cables, etc.
  • Measurement methods and instrumentation architecture
  • ATE and sub-systems design validation and production at speed testing
  • AI and its role in T&M

Tutorial topic suggestion: One box solutions – Why have everything in an oscilloscope?

Modeling of signals on interconnects with high data rates often requires use or extension of analysis techniques originally developed for RF/microwave systems. This track covers signal integrity and signal conditioning analysis techniques for interconnects and passive components of digital and RF/microwave systems as well as the analysis validation with measurements.

Sample topics

  • Signal integrity analysis with RF/Microwave techniques
  • Electromagnetic analysis of interconnects
  • Interconnect analysis validation with measurements
  • S-parameters in analysis of broadband interconnect systems
  • RF/microwave techniques for digital interconnects (e.g. de-embedding, equalization, filtration)
  • Modeling of Embedded passive components (e.g., capacitors, inductors, delay lines)
  • Analysis of losses, dispersion, coupling and mode conversion in interconnects
  • Effects of discontinuities in interconnects (e.g., vias, connectors, launches, transitions, serpentines)
  • Systematic optimization methodology for achieving IEEE P370 signal integrity
  • Hybrid Media breakout section design and modeling for flex and low-loss cabling
  • PHY channel development and characterization for 56G and 112G PAM4 modulated signaling
  • EM modeling of PCB traces/vias, sockets, and connectors and channels
    • EM Modeling and PCB/PCB System mode conversion
  • How to simulate PI and SI on a PCB
    • Board layout techniques for PI and SI
    • PI and SI simulation automation and screening
  • Via pin-field design and optimization

The goal of this track is to enable fast, accurate design and verification of microelectronic circuits and systems by creating machine-learning algorithms to derive models for electronics and system design automation. Unlike traditional programming approaches that have knowledge embedded in complex algorithms and mathematical models, machine-learning uses simple algorithms and models, but with numerous parameters, that are intensively trained with complex data sets. This track explores applications where machine-learning approaches provide alternative solutions to traditional methods, and offer new solutions to challenging problems. Primary foci will be behavioral models, optimization for electronics design, and system analytics with machine learning techniques.

Sample topics

  • Static and dynamic neural network models for high speed channels and SerDes
  • Channel and SerDes performance optimization using PCA or CCA
  • System identification and Volterra Series for non-linear circuits and channel models
  • ML and DoE techniques for optimizing designs with numerous parameter options
  • Generative and Bayesian surrogate models for response surface approximation
  • Machine learning for proactive hardware failure predictions
  • Supervised and un-supervised deep learning for hardware system performance tuning
  • ML techniques for improved rational function model extraction from S-parameters
  • GPU/TPU accelerated SerDes and channel simulation
  • Automated high speed PCB layout design using deep learning
  • ML model portability & reusability across tools and tool flows
  • Training and inference tradeoffs for speed and accuracy
  • Forensic side channel attack detection using power noise analysis with machine learning techniques

Extended Abstract Deadline: July 26, 2019