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This Agenda-at-a-Glance shows a sampling of the wide variety and technical depth of sessions that will be offered at DesignCon 2020 conference.
Visit the full conference schedule to see all 120+ sessions offered across 14 tracks and three conference days.

TIMETuesday, January 28
9:00 a.m. -
11:50 a.m.

Four 3-hour Tutorials including

  • "Open-Source Software Tools for Signal Integrity" in track 13
  • "Design & Verification for High-Speed I/Os at 10- to 112-Gbps with Jitter, Signal Integrity & Power Optimization" in track 8

Three full-day Boot Camps including

  • "Relating SI & PI for High-Speed Digital Boards: FPGA DDR4 Case Study" in track 6
12:00 p.m. -
12:45 p.m.
OPEN TO ALL – Keynote to Be Announced
12:30 p.m. -
1:30 p.m.
Networking Lunch
1:30 p.m. -
4:30 p.m.
Four 3-hour Tutorials including
  • "Introduction to the IEEE P370 Standard & Its Applications for High Speed Interconnect Characterization" in track 12
  • "Electronic/Photonic IC Design for 5G RF Applications" in track 3
  • Three full-day Boot Camps including "Under the Hood: Understand the Software that Drives Electromagnetic Simulation Tools" in track 13
4:45 p.m. -
6:00 p.m.

OPEN TO ALL – Three 75-minute Panel Discussions covering

  • "Succeeding with Next-Generation AMI Models & Analysis" in track 2
  • "Machine Learning" in track 14
  • "The Case of the Closing Eyes: PAM is the Answer, or Not?" in track 8
TIMEWednesday, January 29
8:00 a.m. -
8:45 a.m.

Seven 45-minute Technical Sessions including

  • "Preparing to Test & Avoid Pitfalls in Your USB4 Implementations" in track 12
  • "The Hidden Challenges in 112-Gb Channel Design & Modeling" in track 13
  • "New USB-C Alternate Mode for VR Headset:Design, Optimization & Validation" in track 1
9:00 a.m. -
9:45 a.m.

Seven 45-minute Technical Sessions including

  • "A Practical Method for 3D-Modeling of Glass Weave" in track 13
  • "End-to-End System-Level Simulations with Retimers for PCIe Gen5 & CXL: A How-To Guide" in track 6
  • "Achieving a Robust Power Integrity Solution While Integrating Multiple IPs" in track 10
10:00 a.m. -
10:45 a.m.
OPEN TO ALL – Keynote to Be Announced
11:00 a.m. -
11:45 a.m.

Seven 45-minute Technical Sessions including

  • "Simulation Methodologies of Power Supply Noise Induced Jitter for Systems with Multiple Power Domains" in track 2
  • "Current Distribution, Resistance & Inductance in Power Connectors" in track 10
  • "Leveraging IBIS-AMI Simulations for Optimized Architectural Design in PCIe5 PHY" in track 6
12:00 p.m. -
12:45 p.m.

Seven 45-minute Technical Sessions including

  • "End-to-end FEC Performance Analysis for Multi-Part PAM4 Systems " in track 9
  • "Optimization of Material Characterization & Tolerance Design on Differential Stripline" in track 4
  • "A System-Level Power Integrity Study of Multi-Domain Power Supply Noise Coupling" in track 1
1:00 p.m. -
1:45 p.m.
Networking Lunch
2:00 p.m. -
2:40 p.m.

Seven 45-minute Technical Sessions including

  • "Automatic Channel Condition Detection & Tuning Using Machine Learning Surrogate Models for 56G PAM4 Channels" in track 14
  • "Novel Approach to Finding the Effective Insertion Loss Noise (EILN)" in track 7
  • "Modular Platform Design & Optimization for PCIe 5.0 IPs Validation" in track 6
2:50 p.m. -
3:30 p.m.

Seven 45-minute Technical Sessions including

  • "Measuring Oscilloscope Voltage Probe Performance" in track 12
  • "PDN Induced Jitter Analysis in High Speed NAND Flash Memory Interface" in track 5
  • "Component Design Specification Study for Electrical Serial Links Beyond 112G" in track 7
3:45 p.m. -
5:00 p.m.

OPEN TO ALL – Three 75-minute Panel Discussions covering

  • "Next Gen Materials for High-Speed Digital Design" in track 4
  • "Enabling New Architectures: An Update on OIF's CEI-112G Electrical Interfaces" in track 7
  • "800G & Beyond: Optical Transceiver Technology" in track 3
TIMEThursday, January 30
8:00 a.m. -
8:45 a.m.

Seven 45-minute Technical Sessions including

  • "Equivalent-Time Sampling Oscilloscope Aliasing Analysis" in track 12
  • "A Statistical Modeling Approach for FEC-Encoded High-Speed Wireline Links" in track 8
  • "LPDDR4 Eye-Mask Violation Induced by SSN: Problem/Solution for Neural Compute Engine Package Design" in track 1
9:00 a.m. -
9:45 a.m.

Seven 45-minute Technical Sessions including

  • "Accurate Simulation & Measurement Correlation of Power Supply Noise Coupling & Induced Jitter for High-Speed SerDes" in track 6
  • "Millimeter-Wave Surface Mount Antennas for High-Speed Plastic Fiber Data Transport" in track 3
  • "Crosstalk & Return Loss Budget Trade-Offs Among Different Sections in the SerDes Channel" in track 13
10:00 a.m. -
10:45 a.m.
OPEN TO ALL – Keynote to Be Announced
11:00 a.m. -
11:45 a.m.

Seven 45-minute Technical Sessions including

  • "EDA Flows & Modeling Approaches to Study Analog/Digital Coupling in Semiconductor Products" in track 1
  • "DARPA Chiplet Interconnect Characterization of Build-up & Silicon Interposers" in track 13
  • "Evolution of Transceiver On-Die Termination Models for IBIS-AMI & COM" in track 7
12:00 p.m. -
12:45 p.m.

Seven 45-minute Technical Sessions including

  • "A Method for Dynamic Load Current Testing with a Benchtop Power Supply" in track 12
  • "Accelerate Interposer Design Efficiency Using Neural Networks & Genetic Algorithms" in track 14
  • "Impedance Mask-Based PDN Specifications for Memory Modules & PCBs" in track 10
1:00 p.m. -
1:45 p.m.
Networking Lunch
2:00 p.m. -
2:40 p.m.

Seven 45-minute Technical Sessions including

  • "Power Delivery Improvement & Noise Reduction Using Ultra-Thin (8um) PCB Layers: Simulation, Board Measurements & Practice" in track 4
  • "Optimized Wireless System Design with Minimal RFI Using Antenna Near Field Approach" in track 11
  • "Real-Time Jitter Analysis Using Hardware Based Clock Recovery & Serial Pattern Trigger" in track 8
2:50 p.m. -
3:30 p.m.

Seven 45-minute Technical Sessions including

  • "COM & Reference Transmitter/Receiver/Package for 106/112-Gbps Long-Reach & Chip-to-Chip Links " in track 9
  • "High-Speed Differential Via Characterization: Numerical Simulation & Measurement Validation with De-embedding" in track 13
  • "Self-Evolution Cascade Deep Learning for SerDes Adaptive Equalization" in track 14
3:45 p.m. -
5:00 p.m.

OPEN TO ALL – Three 75-minute Panel Discussions covering

  • "What is Needed for the Next Speed Node Past 112 Gbps & up to 224 Gbps?" in track 9
  • "PCIe 32G & 64G: System Design & Test Challenges" in track 7
  • "Electronic Design Automation Roadmap for Machine Learning & AI Standardization" in track 14