• Conference
    Jan 30-Feb 1, 2018
  • Expo
    Jan 31-Feb 1, 2018
  • Santa Clara Convention
    Center 
    | Santa Clara, CA

2018 Technical Program Committee

The DesignCon 2018 Technical Program Committee (TPC) is comprised of more than 90 leading experts in all levels of electronic design — chip, board, package, and system. These accomplished engineers and executives from top companies such as Cisco, Cadence, Tektronix, Google, Apple, and Intel rigorously review all call-for-paper submissions to develop a conference of the highest quality and industry relevance. Technical papers are then reviewed by the TPC to maintain DesignCon's strict standard for excellence before they become part of the conference proceedings.

The TPC's dedication and expertise helps make DesignCon the nation's premier conference for chip, board, and systems design engineers.

A - E

Brice Achkir, Cisco Distinguished Eng./Sr Eng. Director, Cisco Systems
Joseph Aday, Principal Electrical Engineer, Raytheon
Maria Agoston, Principal Engineer, Tektronix
Kunia Aihara, Staff Hardware Developmenet Engineer, Infinera
Ravinder Ajmani*, Technologist, Electronic Design, Western Digital
John Andresakis, Director of Technical Marketing, Park Electrochemical
Yianni Antoniades, Senior Staff EE, Winchester Electronics Corporation
Rula Bakleh, SI/PI Consultant , Teraspeed Consulting - A Division of Samtec
Heidi Barnes*, SI and PI Engineer, Keysight
Wendem Beyene*, Technical Director, Rambus
Luis Boluna, Sr. Applications Engineer, Keysight Technologies
Bradley Brim*, Product Engineer Architect, Cadence
David Brunker*, Technical Fellow, Molex
Robert Carter*, Vice President, Technology and Busienss Development, Oak-Mitsui Tech
Chris Cheng, Distinguished Technologist, HP Enterprise
Sam Chitwood*, Product Engineer, Cadence
Daehyun Chung, Manager, Hardware Engineering, NVIDIA
Antonio Ciccomancini Scogna, Principal Engineer, Samsung Electronics
Tom Cohen, Principal Engineer, Amphenol
O.J. Danzy, Senior Application Engineer, Keysight
Jan De Geest, Senior Staff SI R&D Engineer, Amphenol
Jay Diepenbrock, Consultant, Consultant
Vladimir Dmitriev-Zdorov, Principal Engineer, Mentor Graphics
Greg Edlund, Senior Engineer, IBM
Jason Ellison, Signal Integrity Engineer, The Siemon Company

F - J

Sanjeev Gupta*, Sr. R&D Manager, FIT
Robert Haller*, Senior Principal Engineer, Extreme Networks
Gert Havermann, Signal Integrity Engineer, HARTING AG&Co.KG
Allen F Horn III*, Associate Research Fellow, Rogers
Rockwell Hsu, Technical Leader, Cisco
Seunghyun Hwang, Sr. SI/PI Engineer, Nvidia

K - O

Namhoon Kim, Master SI Engineer, Broadcom
Ravi Kollipara*, Technical Director, Rambus
Beomtaek Lee, Senior Principal Engineer, Intel Corporation
Joy Li*, R&D manager, Cadence Design Systems
Mike Li*, Fellow, Intel
Zhe Li*, Engineer, Waymo
Cathy Liu*, R&D Director, Broadcom Limited
Chris Loberg*, Sr. Marketing Manager, Tektronix
Om Mandhana, Staff Services AE, Cadence design Systems
Henri Maramis*, President/CEO, Signata
Jon Martens, Fellow, Anritsu
Scott McMorrow, CTO SIgnal Integrity Group, Samtec
Mehdi Mechaik*, ENgineer, Cadence
Ted Mido, Principal Engineer , Synopsys
Jose Moreira*, Senior Staff Engineer, Advantest
Zhen Mu, Sr. Principal Product Enginner, Cadence
Jim Nadolny, Engineering Manager, Samtec
Nechan Naicker, Technical Director, Cirtech EDA (Pty) Ltd
Alfred Neves*, Chief Technologist, Wild River Technology
George Noh*, Director of Marketing and Sales, Holt IC
Istvan Novak, Senior Principle Engineer, Oracle
Chudy Nwachukwu, Finance, Data Center Infrastructure Group, Hewlett Packard
Dan Oh, Vice President, Samsung

P - T

Vishram Pandit*, Technical Lead, Power/Signal Integrity and EMC, Intel
Jongbae Park, Signal Integrity, Apple
Peter Pupalaikis*, Vice President, Technology Development, Teledyne LeCroy
Fangyi Rao, Master Engineer, Keysight
Lee Ritchey, President, Speeding Edge
Gerardo Romo-Luevano, Sr. Staff Engineer/Manager, Qualcomm Technologies, Inc
Steve Sandler, Managing Director, PICOTEST
Venkat Satagopan, Staff Signal Integrity Engineer, Qualcomm Technologies, Inc.
Chris Scholz, Product Manager, Rohde & Schwarz
Christian Schuster, Professor, Hamburg University of Technology (TUHH))
Stefaan Sercu, SI R&D engineer, Samtec
Masashi Shimanouchi, SOC Design Engineer, Intel
Yuriy Shlepnev*, President, Simberian Inc.
Bert Simonovich, President, Lamsim Enterprises
Chad Smutzer, Senior Engineer, Mayo Clinic
Mike Steinberger, Lead Architect, Serial Channel Products, SiSoft
Ransom Stephens*, Sage, Ransom's Notes
Suresh Subramaniam*, Director of Engineering, Whizz Systems
Donald Telian, Consultant, SiGuys
Lars Thon*, Consultant, LT Engineering
Hing (Thomas) To*, Technical Director, Xilinx
Peter Tomaszewski*, Sr Field Applications Engineer, Tektronix

U - Z

Badhri Uppiliappan, Senior Staff CAD Engineer, Analog Devices
Ambrish Varma, Sr. Principal Software Engineer, Cadence Design Systems
Harald von Sosen, Scientist, Synopsys
Michael Vrazel, Systems and DV Manager, Texas Instruments
Min Wang*, Technical Lead Manager, Alphabet / Waymo
Yong Wang*, Sr. Director, Xilinx Inc.
Scott Wedge*, Prinicpal Engineer, Synopsys
Todd Westerhoff*, VP, Semiconductor Relations, SiSoft
Ken Willis, Product Engineering Director, Cadence
Markus Witte, Signal Integrity Manager, HARTING AG
Randy Wolff, Principal Engineer, Silicon SI Team Lead, Micron Technology
Hsinho Wu*, Design Engineer, Intel
Chris Wyland*, Sr. Staff Hardware Engineer, Juniper Networks
Mobashar Yazdani*, Strategic Semiconductor Manager, Google
Iliya Zamek*, Consultant, ZI_Consulting
Geoffrey Zhang, Distinguished Engineer, Supervisor , Xilinx
Pavel Zivny, Domain Expert, Tektronix

*Indicates 2018 Track Chair