Technologies such as 400G Ethernet (IEEE P802.3bs) are driving I/O interconnect technologies including PCI Express to 32GT/s in the 5th generation of that standard. Concurrent computing needs, which are elevating co-processor components to the same computer architectural hierarchy as the CPU, are being developed in the Cache Coherent Interconnect for Accelerators (CCIX) consortium and are touching speeds today of 20 and 25GT/s. With this increase in digital transmission speed, the increase in throughput is accompanied by significant signal integrity challenges related to transmitter signal quality, connector crosstalk, receiver jitter sensitivity, and overall channel insertion loss around the Nyquist frequency at which each of these standards operate. In this session, we will bring you the latest information on what Keysight is doing to help develop standards like PCI Express 5.0 as well as other similar standards as far as physical layer testing including transmitter, receiver, and channel testing. In addition, we will describe the latest approach to achieving compliance that uses the same software tools you use for device characterization, but with data provided by simulation instead of physical measurement. The simulation mimics a real hardware test bench and emits the same waveforms the oscilloscope app expects when testing in the lab, which allows for the verification of pre-manufacture simulated design with the actual post-manufacture prototype.