• Conference
    Jan 29–31, 2019
  • Expo
    Jan 30–31, 2019
  • Santa Clara Convention
    | Santa Clara, CA

Keysight Education Forum

Gather new methods and techniques from the experts at Keysight Technologies during their FREE education workshops—see below schedule. Or visit their booth #725 on the Expo Floor to find out more about their latest products, services, and offerings!

DAY 1 - Wednesday, January 31

The Single Pulse Response demonstrates the impact a channel has on a single pulse. It reveals a lot of information about the behavior of interconnects, including channel loss, reflections and performance of the equalization. Unlike an eye diagram, which gives you final insight into the margin you have available, the Single Pulse Response is a diagnostic method to extract the information you need to improve your margin. In this session, you will learn about simulating the SPR method with Keysight’s Advanced Design System (ADS 2017), analyzing the result in both time and frequency domain, and how it can be applied to modern PAM4 signaling challenges.

Chun-ting "Tim" Wang Lee

Data analytics can play a valuable role in the T&M world by accelerating design simulation, analysis, validation, compliance testing and manufacturing. Effective data analytics tools can help engineers improve their design of experiments and reduce the design cycle time - ultimately saving money and enabling your team to get to market faster. This session explains how modern visualization tools provide critical insights and accelerate new designs.

Brad Doerr
Ailee Grumbine

Most 400G links used in high-speed datacom applications utilize signaling formats such as pulse amplitude modulation 4-level (PAM4) to achieve design goals defined in draft standards such as 400G Ethernet (IEEE 802.3bs and IEEE 802.3cd) and OIF-CEI-56G. The Standards are now stable and nearing ratification, but we know it is often difficult for engineers to stay on top of all the recent changes. Attend this session to learn about the latest updates to new measurements performed on electrical and optical PAM-4 transmitters, and discover new tools that will help you characterize and debug your 400G designs quickly and accurately.

Greg LeCheminant
Robert Sleigh

As the working groups developing “400G” data center networking standards are finishing up these documents, SerDes and optical module vendors are moving from characterizing initial prototypes on evaluation boards to prototyping the first full operational links. As can be expected with the revolutionary change in modulation from NRZ to PAM-4, this can be challenging. This session will cover what we thought we knew about deploying this new format, and surprises we are learning along the way, including measurement challenges characterizing the performance and verifying compliance to the new standards.

Steve Sekel

Day 2 - Thursday, February 1

The USB Type-CTM connector is being used in portable device designs because of power networking capabilities as well as for its high speed digital transport using USB 3.1, Thunderbolt, and DisplayPort technologies. Though flexible, the Type C interface brings the measurement challenges of multiple standards as well as the complexities of device control to the validation task. This presentation will deal exclusively on how to control the USB Type-CTM interface using a dedicated core solution set. The viewer will understand fundamental capabilities of the interface and how each of the challenges can be addressed to fully characterize any USB Type-CTM device.

Brian Fetz

Technologies such as 400G Ethernet (IEEE P802.3bs) are driving I/O interconnect technologies including PCI Express to 32GT/s in the 5th generation of that standard. Concurrent computing needs, which are elevating co-processor components to the same computer architectural hierarchy as the CPU, are being developed in the Cache Coherent Interconnect for Accelerators (CCIX) consortium and are touching speeds today of 20 and 25GT/s. With this increase in digital transmission speed, the increase in throughput is accompanied by significant signal integrity challenges related to transmitter signal quality, connector crosstalk, receiver jitter sensitivity, and overall channel insertion loss around the Nyquist frequency at which each of these standards operate. In this session, we will bring you the latest information on what Keysight is doing to help develop standards like PCI Express 5.0 as well as other similar standards as far as physical layer testing including transmitter, receiver, and channel testing. In addition, we will describe the latest approach to achieving compliance that uses the same software tools you use for device characterization, but with data provided by simulation instead of physical measurement. The simulation mimics a real hardware test bench and emits the same waveforms the oscilloscope app expects when testing in the lab, which allows for the verification of pre-manufacture simulated design with the actual post-manufacture prototype.

Pegah Alavi
Rick Eads

It is no trivial task to make a good measurement. It requires careful calibration of the ports on the instrument, and appropriate application of fixture removal to the device under test. If treated with care, the result of your hard work is more than an accurate high frequency behavioral model of a channel. It is a gateway to a better understanding of serial link performance and channel operating margin. Given proper measurement, analysis and simulation tools, you will be able to extract the material properties, create a channel model and optimize your channel for minimal bit errors. Moreover, with the help of the single pulse response analysis method, the effect of equalization can be studied and configured. In this session, you will learn to establish a robust measurement and simulation workflow and get the most signal integrity insight out of your everyday measurement and simulation process.

Mike Resso
Chun-ting "Tim" Wang Lee

DDR4 was the first DRAM technology to break the High Speed Digital paradigm that focuses on signal timing and Voh/Vol/Vih/Vil based noise margin analysis. DDR4 speeds demanded an approach more like what’s used in specifying, designing and testing high speed serial interfaces like SATA, USB 3.0 and PCI-Express (up to Gen 3). Timing and voltage thresholds are replaced by eye diagrams, bit error rates and statistical analysis of random jitter and noise, closing a gap between the DDR specification and the behavior of real systems that opened once DDR3 exceeded 1600MT/s. Many memory designers are still climbing this learning curve that is essential to getting the best performance from DDR4 designs at minimum design risk and cost. Right on the heels of DDR4, DDR5 moves the bar even higher to reach speeds where the data eye is completely closed, requiring advanced equalization techniques to open the eye and assure reliable data transfer. This session will help engineers better understand the concepts underlying the DDR4 specification and get the maximum benefits of having a specification that models real system behavior. Then we will extend the discussion to DDR5, to prepare architects, design, and test engineers to take full advantage of its advanced capabilities.

Perry Keller